1. Field of the Invention
The present invention relates to a gate oxide breakdown-withstanding power switch structure applied to SRAM, particularly to a power switch using two different gate-oxide thicknesses or two different threshold voltages to prevent a power switch gate-oxide breakdown from happening.
2. Description of the Related Art
More embedded memories are integrated on chips to support more powerful computation engines, leading to low-power and reliable memory design techniques being more important. At present, most of advanced SRAMs (Static Random Access Memory) utilize a power switch to reduce leakage current and power consumption in the standby/sleep mode of SRAM. Refer to FIG. 1 a diagram schematically showing that a conventional power switch is applied to SRAM. The power switch structure comprises a P-type transistor 10 and an N-type transistor 12. The source of the P-type transistor 10 and the drain of the N-type transistor 12 are connected with a voltage source VDD. The drain of the P-type transistor 10 and the source of the N-type transistor 12 are connected with the voltage terminal VVDD of an SRAM cell array 14. The other terminal of the SRAM cell array 14 is connected with the ground GND. The gate of the P-type transistor 10 receives a control signal HPG. If the control signal is at a low level, the P-type transistor 10 turns on, and VDD will charge VVDD to a potential level identical to that of VDD. At this moment, the cell array 14 is allowed to be read or written. If the control signal is at a high level, the P-type transistor 10 turns off, and the voltage level of VVDD is lower than the gate voltage level of the N-type transistor 12 by a threshold voltage. The cell array 14 is in a standby mode or a sleep mode. By turning off P-type transistor 10, leakage current of the cell array 14 can be significantly decreased. The N-type transistor 12 is used to bias VVDD of the cell array 14 at a proper voltage level for data retention.
The gate oxide thickness becomes thinner as technology scaling. However, the voltage level of power supply remains unchanged. These result in a high gate-oxide electric-field and gate-oxide breakdown. Therefore, gate-oxide breakdown becomes a critical factor in sub-100 nm SRAM design.
The breakdown or damage of the gate oxide of a power switch will seriously decrease the noise margin, stability, performance and reliability. Refer to FIGS. 1-3. In the active state of SRAM, the normal P-type transistor 10 turns on to provide a voltage source of 0.9V for the active cell array 14, as shown in FIG. 2. Once gate-oxide breakdown of the P-type transistor 10 occurs, a leakage path appears between the gate and drain of the P-type transistor 10, and this conduction path can be expressed as an equivalent resistance. If the equivalent resistance has a greater value, such 108Ω, VVDD voltage level of the cell array 14 is still 0.9V, and the impact of gate-oxide breakdown on SRAM is negligible. When gate-oxide breakdown is more serious and the equivalent resistance has a smaller value, such 104Ω, VVDD voltage level of the cell array 14 is only 0.1V. In such a case, gate-oxide breakdown of the P-type transistor 10 severely degrade noise margin, stability and performance of SRAM. As shown in FIG. 3, when SRAM is in standby or sleep mode, the normal P-type transistor 10 turns off. Once gate-oxide breakdown of the P-type transistor 10 occurs, a leakage path appears between the gate and drain of the P-type transistor 10. Referring to FIG. 3, the VVDD voltage level of the cell array 14 increases as equivalent resistance decreasing. This phenomenon leads to leakage current of the cell array 14 increasing.
Accordingly, the present invention proposes a gate oxide breakdown-withstanding power switch structure to overcome the abovementioned problem.